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radar receive path afe: 6-channel lna/pga/aaf with adc AD8283 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 6 channels of lna, pga, aaf 1 channel of direct-to-adc programmable gain amplifier (pga) includes low noise preamplifier (lna) spi-programmable gain = 16 db to 34 db in 6 db steps antialiasing filter (aaf) programmable third-order low-pass elliptic filter (lpf) from 1 mhz to 12 mhz analog-to-digital converter (adc) 12 bits of accuracy up to 80 msps snr = 67 db sfdr = 68 db low power, 170 mw per channel at 12 bits/80 msps low noise, 3.5 nv/hz maximum of input referred voltage noise power-down mode 72-lead, 10 mm 10 mm, lfcsp package specified from ?40c to +105c qualified for automotive applications applications automotive radar adaptive cruise control collision avoidance blind spot detection self-parking electronic bumper functional block diagram reference spi ina+ ina? inb+ inc+ inc? inb? ind+ ind? ine+ ine? inf+ inf? 12-bit adc dsync d[0:11] zsel pdwn muxa aaf AD8283 aaf aaf aaf aaf aaf drv pga lna pga lna pga lna pga lna pga lna pga lna cs avdd33x avdd18x inadc+ inadc? rbias vref dvdd33x dvdd18x sclk sdio aux clk+ clk? 09795-001 mux figure 1. general description the AD8283 is designed for low cost, low power, compact size, flexibility, and ease of use. it contains six channels of a low noise preamplifier (lna) with a programmable gain amplifier (pga) and an antialiasing filter (aaf) plus one direct-to-adc channel, all integrated with a single 12-bit analog-to-digital converter (adc). each channel features a gain range of 16 db to 34 db in 6 db increments and an adc with a conversion rate of up to 80 msps. the combined input-referred noise voltage of the entire channel is 3.5 nv/hz at maximum gain. the channel is optimized for dynamic performance and low power in applications where a small package size is critical. fabricated in an advanced cmos process, the AD8283 is available in a 10 mm 10 mm, rohs-compliant, 72-lead lfcsp. it is specified over the automotive temperature range of ?40c to +105c.
AD8283 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? ac specifications.......................................................................... 3 ? digital specifications ................................................................... 5 ? switching specifications .............................................................. 6 ? absolute maximum ratings............................................................ 7 ? esd caution.................................................................................. 7 ? pin configuration and function descriptions............................. 8 ? typical performance characteristics ........................................... 10 ? theory of operation ....................................................................... 14 ? radar receive path afe............................................................ 14 ? channel overview...................................................................... 15 ? adc ............................................................................................. 16 ? clock input considerations ...................................................... 16 ? clock duty cycle considerations ............................................ 17 ? clock jitter considerations....................................................... 17 ? sdio pin...................................................................................... 17 ? sclk pin ..................................................................................... 17 ? cs pin .......................................................................................... 17 ? rbias pin.................................................................................... 18 ? voltage reference ....................................................................... 18 ? power and ground recommendations ................................... 18 ? exposed paddle thermal heat slug recommendations ...... 18 ? serial peripheral interface (spi) ................................................... 19 ? hardware interface..................................................................... 19 ? memory map .................................................................................. 21 ? reading the memory map table.............................................. 21 ? logic levels................................................................................. 21 ? reserved locations .................................................................... 21 ? default values ............................................................................. 21 ? application diagrams .................................................................... 25 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? automotive products ................................................................. 27 ? revision history 4/11revision 0: initial version
AD8283 rev. 0 | page 3 of 28 specifications ac specifications avdd18x = 1.8 v, avdd33x = 3.3 v, dvdd18x = 1.8 v, dvdd33x = 3.3 v, 1.024 v internal adc reference, f in = 2.5 mhz, f sample = 80 msps, r s = 50 , lna + pga gain = 34 db, lpf cutoff = f samplech /4, full channel mode, 12-bit operation, temperature = ?40c to +105c, unless otherwise noted. table 1. AD8283w parameter 1 conditions min typ max unit analog channel characteristics lna, pga, and aaf channel gain 16/22/28/34 db gain range 18 db gain error ?1.25 +1.25 db input voltage range channel gain =16 db 0.25 v p-p channel gain = 22 db 0.125 channel gain = 28 db 0.0625 channel gain = 34 db 0.03125 input resistance 200 input impedance selected 0.180 0.230 0.280 k 200 k input impedance selected 160 200 240 input capacitance 22 pf input-referred voltage noise max gain at1 mhz 1.85 nv/hz min gain at 1 mhz 6.03 nv/hz noise figure max gain, r s = 50 , unterminated 7.1 db max gain, r s =r in = 50 12.7 db output offset gain = 16 db ?60 +60 lsb gain = 34 db ?250 +250 lsb aaf low-pass filter cutoff ?3 db, programmable 1.0 to 12.0 mhz aaf low-pass filter cutoff tolerance after filter autotune ?10 5 +10 % aaf attenuation in stop band third order elliptical filter 2 cutoff 30 db 3 cutoff 40 db group delay variation filter set at 2 mhz 400 ns channel-to-channel phase variation frequencies up to ?3 db ?5 0.5 +5 degrees ? of ?3 db frequency ?1 +1 degrees channel-to-channel gain matching frequencies up to ?3 db ?0.5 0.1 +0.5 db 1/4 of ?3 db frequency ?0.25 +0.25 db 1 db compression relative to output 9.8 dbm crosstalk ?70 ?55 dbc power supply avdd18x 1.7 1.8 1.9 v avdd33x 3.1 3.3 3.5 v dvdd18x 1.7 1.8 1.9 v dvdd33x 3.1 3.3 3.5 v i avdd18 full-channel mode 190 ma i avdd33 full-channel mode 190 ma i dvdd18 22 ma i dvdd33 2 ma total power dissipation C per channel full-channel mode, no signal, typical supply voltage maximum supply current; excludes output current 170 mw power-down dissipation 5 mw power supply rejection ratio (psrr) relative to input 1.6 mv/v
AD8283 rev. 0 | page 4 of 28 AD8283w parameter 1 conditions min typ max unit adc resolution 12 bits max sample rate 80 msps signal-to-noise ratio (snr) f in = 1 mhz 68.5 db signal-to-noise and distortion (sinad) 66 db snrfs 68 db differential nonlinearity (dnl) guaranteed no missing codes 1 lsb integral nonlinearity (inl) 10 lsb effective number of bits (enob) 10.67 lsb adc output characteristics maximum cap load per bit 20 pf i dvdd33 peak current with cap load peak current per bit when driving a 20 pf load; can be programmed via the spi port if required 40 ma adc reference output voltage error vref = 1.024 v 25 mv load regulation at 1.0 ma, vref = 1.024 v 2 mv input resistance 6 k full channel characteristics lna, pga, aaf, and adc snrfs f in = 1 mhz gain = 16 db 68 db gain = 22 db 68 db gain = 28 db 68 db gain = 34 db 66 db sinad f in = 1 mhz gain = 16 db 67 db gain = 22 db 68 db gain = 28 db 67 db gain = 34 db 66 db sfdr f in = 1 mhz gain = 16 db 68 db gain = 22 db 74 db gain = 28 db 74 db gain = 34 db 73 db harmonic distortion second harmonic f in =1 mhz at ?10 dbfs, gain = 16 db ?70 dbc f in =1 mhz at ?10 dbfs, gain = 34 db ?70 dbc third harmonic f in =1 mhz at ?10 dbfs, gain = 16 db ?66 dbc f in =1 mhz at ?10 dbfs, gain = 34 db ?75 dbc im3 distortion f in1 = 1 mhz, f f in2 = 1.1 mhz, ?1 dbfs, gain = 34 db ?69 dbc gain response time 600 ns overdrive recovery time 200 ns 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed.
AD8283 rev. 0 | page 5 of 28 digital specifications avdd18x = 1.8 v, avdd33 = 3.3 v, dvdd18 = 1.8 v, dvdd33 = 3.3 v, 1.024 v internal adc reference, f in = 2.5 mhz, f sample = 80 msps, r s = 50 , lna + pga gain = 34 db, lpf cutoff = f samplech /4, full channel mode, 12-bit operation, temperature = ?40c to +105c, unless otherwise noted. table 2. parameter 1 temperature min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 250 mv p-p input common-mode voltage full 1.2 v input resistance (differential) 25c 20 k input capacitance 25c 1.5 pf logic inputs (pdwn, sclk, aux, muxa, zsel) logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 30 k input capacitance 25c 0.5 pf logic input ( cs ) logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 70 k input capacitance 25c 0.5 pf logic input (sdio) logic 1 voltage full 1.2 dvdd33x + 0.3 v logic 0 voltage full 0 0.3 v input resistance 25c 30 k input capacitance 25c 2 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 3.0 v logic 0 voltage (i ol = 50 a) full 0.3 v logic output (d[11:0], dsync) logic 1 voltage (i oh = 2 ma) full 3.0 v logic 0 voltage (i ol = 2 ma) full 0.05 v 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 specified for lvds and lvpecl only. 3 specified for 13 sdio pins sharing the same connection.
AD8283 rev. 0 | page 6 of 28 switching specifications avdd18x = 1.8 v, avdd33x = 3.3 v, dvdd18x = 1.8 v, dvdd33x = 3.3 v, 1.024 v internal adc reference, f in = 2.5 mhz, f sample = 80 msps, r s = 50 , lna + pga gain = 34 db, lpf cutoff = f samplech /4, full channel mode, 12-bit operation, temperature = ?40c to +105c, unless otherwise noted. table 3. parameter 1 temperature min typ max unit clock clock rate full 10 80 msps clock pulse width high (t eh ) at 80 msps full 6.25 ns clock pulse width low (t el ) at 80 msps full 6.25 ns clock pulse width high (t eh ) at 40 msps full 12.5 ns clock pulse width low (t el ) at 40 msps full 12.5 ns output parameters propagation delay (t pd ) at 80 msps full 1.5 2.5 5.0 ns rise time (t r ) full 1.9 ns fall time (t f ) full 1.2 ns data set-up time (t ds ) at 80 msps full 9.0 10.0 11.0 ns data hold time (t dh ) at 80 msps full 1.5 4.0 5.0 ns data set-up time (t ds ) at 40 msps full 21.5 22.5 23.5 ns data hold time (t dh ) at 40 msps full 1.5 4.0 5.0 ns pipeline latency full 7 clock cycles 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. n ?1 inax n n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n clk? clk+ d[11:0] t pd t eh t el t ds t dh 09795-002 figure 2. timing definitions for switching specifications
AD8283 rev. 0 | page 7 of 28 absolute maximum ratings table 4. parameter with respect to rating electrical avdd18x gnd ?0.3 v to +2.0 v avdd33x gnd ?0.3 v to +3.5 v dvdd18x gnd ?0.3 v to +2.0 v dvdd33x gnd ?0.3 v to +3.5 v analog inputs inx+, inx- gnd ?0.3 v to +3.5 v auxiliary inputs inadc+, inadc- gnd ?0.3 v to +2.0 v digital outputs d[11:0], dsync, sdio gnd ?0.3 v to +3.5 v clk+, clk? gnd ?0.3 v to +3.9 v pdwn, sclk, cs , aux, muxa, zsel gnd ?0.3 v to +3.9 v rbias, vref gnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40c to +105c storage temperature range (ambient) ?65c to +150c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD8283 rev. 0 | page 8 of 28 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc dsync pdwn dvdd18 sclk sdio cs aux muxa zsel test1 test2 dvdd33spi avdd18 avdd33a ina? 17 ina+ 18 nc 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 nc nc avdd33b inb? inb+ avdd33c inc? inc+ avdd33d ind? ind+ avdd33e ine? ine+ avdd33f inf? 35 inf+ 36 nc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 nc test4 dvdd18clk clk+ clk? dvdd33clk avdd33ref vref rbias band apout anout test3 avdd18adc avdd18 inadc+ inadc? nc 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 nc dvdd33drv nc nc d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 dvdd33drv nc notes 1. nc = no connect. do not connect to this pin. 2. the exposed paddle should be tied to analog/digital ground plane. pin 1 indicator AD8283 (top view) 09795-003 figure 3. table 5. pin function descriptions pin no. name description 0 gnd ground. exposed paddle on the bottom side; should be tied to the analog /digital ground plane. 1 nc no connection. pin can be tied to any potential. 2 dsync data out synchronization. 3 pdwn full power-down. logic high overrides spi and powers down the part, logic low allows selection through spi. 4 dvdd18 1.8 v digital supply. 5 sclk serial clock. 6 sdio serial data input/output. 7 cs chip select bar. 8 aux logic high forces to channel adc (inadc+/ inadc?); aux has a higher priority than muxa. 9 muxa logic high forces to channel a unless aux is asserted. 10 zsel input impedance select. logic high overrides spi and se ts it to 200 k; logic low allows selection through spi. 11 test1 pin should not be used; tie to ground. 12 test2 pin should not be used; tie to ground. 13 dvdd33spi 3.3 v digital supply, spi port. 14 avdd18 1.8 v analog supply. 15 avdd33a 3.3 v analog supply, channel a. 16 ina? negative lna analog input for channel a. 17 ina+ positive lna analog input for channel a. 18 nc no connect. pin can be tied to any potential. 19 nc no connect. pin can be tied to any potential. 20 nc no connect. pin can be tied to any potential. 21 avdd33b 3.3 v analog supply, channel b. 22 inb?- negative lna analog input for channel b. 23 inb+ positive lna analog input for channel b. 24 avdd33c 3.3 v analog supply, channel c. 25 inc? negative lna analog input for channel c. 26 inc+ positive lna analog input for channel c.
AD8283 rev. 0 | page 9 of 28 pin no. name description 27 avdd33d 3.3 v analog supply, channel d. 28 ind? negative lna analog input for channel d. 29 ind+ positive lna analog input for channel d. 30 avdd33e 3.3 v analog supply, channel e. 31 ine? negative lna analog input for channel e. 32 ine+ positive lna analog input for channel e. 33 avdd33f 3.3 v analog supply, channel f. 34 inf? negative lna analog input for channel f. 35 inf+ positive lna analog input for channel f. 36 nc no connect, pin can be tied to any potential. 37 nc no connect. pin can be tied to any potential. 38 inadc? negative analog input fo r alternate channel f (adc only). 39 inadc+ positive analog input fo r alternate channel f (adc only). 40 avdd18 1.8 v analog supply. 41 avdd18adc 1.8 v analog supply, adc. 42 test3 pin should not be used; tie to ground. 43 anout analog outputs (debug purposes only). pin should be floated. 44 apout analog outputs (debug purpos es only). pin should be floated. 45 band band gap voltage (debug purposes only). pin should be floated. 46 rbias external resistor to set th e internal adc core bias current. 47 vref voltage reference input/output. 48 avdd33ref 3.3 v analog supply, references. 49 dvdd33clk 3.3 v digital supply, clock. 50 clk- clock input complement. 51 clk+ clock input true. 52 dvdd18clk 1.8 v digital supply, clock. 53 test4 pin should not be used; tie to ground. 54 nc no connect. pin can be tied to any potential. 55 nc no connect. pin can be tied to any potential. 56 dvdd33drv 3.3 v digital supply, output driver. 57 d11 adc data out (msb). 58 d10 adc data out. 59 d9 adc data out. 60 d8 adc data out. 61 d7 adc data out. 62 d6 adc data out. 63 d5 adc data out. 64 d4 adc data out. 65 d3 adc data out. 66 d2 adc data out. 67 d1 adc data out. 68 d0 adc data out (lsb). 69 nc no connect. pin should be left open. 70 nc no connect. pin should be left open. 71 dvdd33drv 3.3 v supply, output driver. 72 nc no connect. pin can be tied to any potential.
AD8283 rev. 0 | page 10 of 28 typical performance characteristics v s = 3.3 v, 1.8 v, t a = 25c, f s = 80 msps, r in =200 k, vref = 1.0 v. (lsb) percentage of devices (%) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 33.50 33.58 33.66 33.74 33.82 33.90 33.98 34.06 34.14 34.22 34.30 34.38 34.46 09795-033 ?40 ?30 ?20 ?10 0 10 20 30 40 50 0.1 1 10 100 gain (db) frequency (mhz) 34db 28db 22db 16db 09795-014 figure 7. gain error histogram (gain = 34 db) figure 4. channel gain vs. frequency percentage of devices (%) (db) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 09795-034 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?15 10 35 60 85 gain error (db) temperature (c) 34db 28db 22db 16db 09795-038 figure 8. channel-to-channel ga in matching (gain = 16 db) figure 5. gain error vs. temperature at all gains percentage of devices (%) 0 1 2 3 4 5 6 7 8 9 10 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 (db) 09795-035 percentage of devices (%) (db) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 16.00 16.08 16.16 16.24 16.32 16.4 16.48 16.56 16.64 16.72 16.8 16.88 16.96 09795-032 figure 9. channel-to-channel gain matching (gain = 34 db) figure 6. gain error histogram (gain = 16 db)
AD8283 rev. 0 | page 11 of 28 0 2000 4000 6000 8000 10000 12000 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 34567 number of hits code 09795-015 figure 10. output referred noise histogram (gain = 16 db) ?7?6?5?4?3?2?101234567 0 1000 2000 3000 4000 5000 6000 7000 number of hits code 09795-016 figure 11. output referred noise histogram (gain = 34 db) 0 5 10 15 0.1 1 10 noise (nv/ hz) frequency (mhz) 22db 28db 34db 16db 09795-030 figure 12. short circuit input- referred noise vs. frequency 40 45 50 55 60 65 70 16 22 28 34 snr/sinad (dbfs) gain (db) snr sinad 09795-017 figure 13. snr vs. gain ?50 ?40 ?30 ?20 ?10 0 10 20 0.1 1 10 100 gain (db) frequency (hz) 12mhz 8mhz 4mhz 2mhz 1mhz 09795-022 figure 14. filter response 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 noise (nv/ hz) frequency (mhz) 22db 16db 28db 34db 09795-031 figure 15. short-circuit output-referred noise vs. frequency
AD8283 rev. 0 | page 12 of 28 0 100 200 300 400 500 600 700 800 900 1000 0.1 1 10 100 del a y (ns) frequency (mhz) 1mhz 2mhz 4mhz 8mhz 12mhz 09795-019 figure 16. group delay vs. frequency ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ? 40 01234567 harmonic (dbc) input frequency (mhz) second ?1dbfs second ?10dbfs third ?1dbfs third ?10dbfs 09795-039 figure 17. harmonic distortion vs. frequency 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 200000 0 50 100 150 200 250 300 350 400 450 500 0.01 0.1 1 10 100 impedance ( ? ) frequency (mhz) 09795-040 figure 18. r in vs. frequency ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 amplitude (v) time (s) 09795-041 figure 19. over drive recovery ch3 1v ch2 500mv m1s 1.25gs/s a ch2 560mv 800ps/pt 2 3 ? mean(c2) 220mv : 220m m: 220m m: 220m :0 freq(c2) 997.8khz : 997.75504k m: 997.8k m: 997.8k :0 mean(c2) 7.177mv : 7.1773964m m: 7177m m: 7.177m :0 le v el 560mv trig holdoff 1.5s sdo analog output 09795-024 figure 20. gain step response 0 5 10 15 20 25 30 0.1 1 10 noise figure (db) frequency (mhz) 34db 50 ? terminated 34db unterminated 09795-042 figure 21. noise fi gure vs. frequency
AD8283 rev. 0 | page 13 of 28 (lsb) percentage of devices (%) 0 1 2 3 4 5 6 7 8 9 10 ?60 ?56 ?52 ?48 ?44 ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 09795-036 0 1 2 3 4 5 6 7 8 9 10 11 12 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 180 200 (lsb) percentage of devices (%) 09795-037 figure 22. channel offset distribution (gain = 16 db) figure 23. channel offset distribution (gain = 34 db)
AD8283 rev. 0 | page 14 of 28 theory of operation radar receive path afe the primary application for the AD8283 is high-speed ramp, frequency modulated, continuous wave radar (hsr-fmcw radar). figure 25 shows a simplified block diagram of an hsr- fmcw radar system. the signal chain requires multiple channels, each including a low noise amplifier (lna), a programmable gain amplifier (pga), an antialiasing filter (aaf), and an analog-to-digital converter (adc). the AD8283 provides all of these key components in a single 10 10 lfcsp package. the performance of each component is designed to meet the demands of an hsr-fmcw radar system. some examples of these performance metrics are the lna noise, pga gain range, aaf cutoff characteristics, and adc sample rate and resolution. the AD8283 includes a multiplexer (mux) in front of the adc as a cost saving alternative to having an adc for each channel. the mux automatically switches between each active channel after each adc sample. the dsync output indicates when channel a data is at the adc output, and data for each active channel follows sequentially with each clock cycle. the effective sample rate for each channel is reduced by a factor equal to the number of active channels. the adc resolution of 12 bits with up to 80 msps sampling satisfies the requirements for most hsr-fmcw approaches. pa dsp antenna vco 12-bit adc aaf aaf aaf pga lna pga lna pga lna AD8283 mux ref. oscillator chirp ramp generator 09795-004 figure 24. radar system overview mux AD8283 mux controller spi interface sdio scl k aaf pga lna pipeline adc third-order elliptical filter ?6db, 0db, 6db, 12db 12-bit 80msps inx+ inx? 22db 200? / 200k ? parallel 3.3v cmos d11:d0 dsync 09795-005 figure 25. simplified block diagram of a single channel
AD8283 rev. 0 | page 15 of 28 channel overview each channel contains an lna, a pga, and an aaf in the signal path. the lna input impedance can be either 200 or 200 k. the pga has selectable gains that result in channel gains ranging from 16 db to 34 db. the aaf has a three-pole elliptical response with a selectable cutoff frequency. the mux is synchronized with the adc and automatically selects the next active channel after the adc acquires a sample. the signal path is fully differential throughout to maximize signal swing and reduce even-order distortion including the lna, which is designed to be driven from a differential signal source. low noise amplifier (lna) good noise performance relies on a proprietary ultralow noise lna at the beginning of the signal chain, which minimizes the noise contributions on the following pga and aaf. the input impedance can be either 200 or 200 k and is selected through the spi port or by the zsel pin. the lna supports differential output voltages as high as 4.0 v p-p with positive and negative excursions of 1.0 v from a common- mode voltage of 1.5 v. with the output saturation level fixed, the channel gain sets the maximum input signal before saturation. low value feedback resistors and the current-driving capability of the output stage allow the lna to achieve a low input- referred noise voltage of 3.5 nv/hz at a channel gain of 34 db. the use of a fully differential topology and negative feedback minimizes second-order distortion. differential signaling enables smaller swings at each output, further reducing third- order distortion. recommendation to achieve the best possible noise performance, it is important to match the impedances seen by the positive and negative inputs. matching the impedances ensures that any common- mode noise is rejected by the signal path. antialiasing filter (aaf) the filter that the signal reaches prior to the adc is used to band limit the signal for antialiasing. the antialiasing filter uses a co mbination of poles and zeros to create a third-order elliptical filter . an elliptical filter is used to achieve a sharp roll off after the cu toff frequency. the filter uses on-chip tuning to trim the capacitors to set the desired cutoff frequency. this tuning method reduces variations in the cutoff frequency due to standard ic process tolerances of resistors and capacitors. the default ?3 db low-pass filter cutoff is 1/3 or 1/4 the adc sample clock rate. the cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the spi. tuning is normally off to avoid changing the capacitor settings during critical times. the tuning circuit is enabled and disabled through the spi. initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or adc sample rate. occasional retuning during an idle time is recommended to compensate for temperature drift. a cut-off range of 1 mhz to 12 mhz is possible. an example follows: ? four channels selected: a, b, c, and aux ? adc clock: 30 mhz ? per channel sample rate = 30/4 = 7.5 msps ? default tuned cutoff frequency = 7.5/4 = 1.88 mhz mux and mux controller the mux is designed to automatically scan through each active channel. the mux remains on each channel for one clock cycle, then switches to the next active channel. the mux switching is synchronized to the adc sampling so that the mux switching and channel settling time do not interfere with adc sampling. as indicated in table 8 , register address 0c, flex mux control, channel a, is usually the first converted input. the one exceptions occurs when channel aux is the sole input (see figure 26 for timing). channel aux is always forced to be the last converted input. unselected codes put the respective channels (lna, pga, and filter) in power-down mode unless register address 0c, bit 6, is set to 1. figure 26 shows the timing of the clock input and data/dsync outputs.
AD8283 rev. 0 | page 16 of 28 n inax n + 1 outa n ? 1 xxxx notes 1. for above configuration register address 0c set to 1010 (channel a, b, c, d, e and f enabled). 2. dsync is always aligned with channel a unless channel a or channel aux is the only channel selected, in which case dsync is not active. 3. there is a seven clock cycle latency from sampling a channel to its digital data being present on the parallel bus pins. outb outc outd oute outf outa n outb clk? clk+ d[11:0] dsync t pd t dh t ds 0 9795-006 figure 26. data and dsync timing adc the AD8283 uses a pipelined adc architecture. the quantized output from each stage is combined into a 12-bit result in the digital correction logic. the pipe lined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. sampling occurs on the rising edge of the clock. the output staging block aligns the data, corrects errors, and passes th e data to the output buffers. clock input considerations for optimum performance, the AD8283 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac-coupled into the clk+ and clk? pins via a transformer or using capacitors. these pins are biased internally and require no additional bias. figure 27 shows the preferred method for clocking the AD8283. a low jitter clock source, such as the valpey fisher oscillator vfac3-bhl-50mhz, is converted from single ended to differential using an rf transformer. the back-to-back schottky diodes across the secondary transformer limit clock excursions into the AD8283 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the AD8283, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsm2812 3.3v 50? 100 ? clk? clk+ adc AD8283 mini-circuits ? adt1-1wt, 1:1z xfmr vfac3 out 09795-007 figure 27. transformer-coupled differential clock if a low jitter clock is available, another option is to ac-couple a differential pecl or lvds signal to the sample clock input pins as shown in and figure 28 and figure 29 . the ad951x/ad952x family of clock drivers offers excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240? 240 ? 50? * clk clk * 50? resistor is optional. clk? clk+ adc AD8283 pecl driver 3.3v out vfac3 ad951x/ad952x family 09795-008 figure 28. differential pecl sample clock 100 ? 0.1f 0.1f 0.1f 0.1f ad951x/ad952x family 50? * clk clk * 50? resistor is optional. clk? clk+ adc AD8283 lvds driver 3.3v out vfac3 09795-009 figure 29. differential lvds sample clock
AD8283 rev. 0 | page 17 of 28 in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, clk+ should be driven directly from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 30). although the clk+ input circuit supply is avdd18, this input is designed to withstand input voltages of up to 3.3 v, making the selection of the drive logic voltage very flexible. the ad951x/ad952x family of parts can be used to provide 3.3 v inputs (see figure 31). in this case, 39 k is not needed. 0.1f 0.1f 0.1f 39k ? 1.8v cmos driver 50 ? * optional 100? 0.1f clk clk * 50? resistor is optional. clk? clk+ adc AD8283 3.3 v out vfac3 ad951x/ad952x family 09795-010 figure 30. single-ended 1.8 v cmos sample clock 0.1f 0.1f cmos driver 3.3v 50 ? * optional 100? 0.1f clk clk * 50? resistor is optional. clk? clk+ adc AD8283 3.3 v out vfac3 0.1f ad951x/ad952x family 09795-011 figure 31. single-ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD8283 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the AD8283. when the dcs is on, noise and distortion performance are nearly flat for a wide range of duty cycles. however, some applications may require the dcs function to be off. if so, keep in mind that the dynamic range performance can be affected when operated in this mode. see table 8 for more details on using this feature. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately eight clock cycles to allow the dll to acquire and lock to the new rate. clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr degradation = 20 log 10[1/2 f a t j ] in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter. if undersampling applications are particularly sensitive to jitter. the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD8283. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources, such as the valpey fisher vfac3 series. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about how jitter performance relates to adcs (visit www.analog.com ). sdio pin the sdio pin is required to operate the spi. it has an internal 30 k pull-down resistor that pulls this pin low and is only 1.8 v tolerant. if applications require that this pin be driven from a 3.3 v logic level, insert a 1 k resistor in series with this pin to limit the current. sclk pin the sclk pin is required to operate the spi port interface. it has an internal 30 k pull-down resistor that pulls this pin low and is both 1.8 v and 3.3 v tolerant. cs pin the cs pin is required to operate the spi port interface. it has an internal 70 k pull-up resistor that pulls this pin high and is both 1.8 v and 3.3 v tolerant. rbias pin to set the internal core bias current of the adc, place a resistor nominally equal to 10.0 k to ground at the rbias pin. using other than the recommended 10.0 k resistor for rbias degrades the performance of the device. therefore, it is imperative that at least a 1.0% tolerance on this resistor be used to achieve consistent performance. voltage reference a stable and accurate 0.5 v voltage reference is built into the AD8283. this is gained up internally by a factor of 2, setting vref to 1.0 v, which results in a full-scale differential input span of 2.0 v p-p for the adc. vref is set internally by default, but the vref pin can be driven externally with a 1.0 v
AD8283 rev. 0 | page 18 of 28 reference to achieve more accuracy. however, this device does not support adc full-scale ranges below 2.0 v p-p. when applying the decoupling capacitors to the vref pin, use ceramic low-esr capacitors. these capacitors should be close to the reference pin and on the same layer of the pcb as the AD8283. the vref pin should have both a 0.1 f capacitor and a 1 f capacitor connected in parallel to the analog ground. these capacitor values are recommended for the adc to properly settle and acquire the next valid sample. power and ground recommendations when connecting power to the AD8283, it is recommended that two separate 1.8 v supplies and two separate 3.3 v supplies be used: one for analog 1.8 v (avdd18x) and digital 1.8 v (dvdd18x) and one for analog 3.3 v (avdd33x) and digital 3.3 v (dvdd33x). if only one supply is available for both analog and digital, for example, avdd18x and dvdd18x, it should be routed to the avdd18x first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the dvdd18x. the same is true for the analog and digital 3.3 v supplies. the user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts, with minimal trace lengths. a single pc board ground plane should be sufficient when using the AD8283. with proper decoupling and smart partitioning of the pc boards analog, digital, and clock sections, optimum performance can be achieved easily. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD8283. an exposed continuous copper plane on the pcb should mate to the AD8283 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged with nonconductive epoxy. to maximize the coverage and adhesion between the device and pcb, partition the continuous copper pad by overlaying a silk- screen or solder mask to divide this into several uniform sections. this ensures several tie points between the two during the reflow process. using one continuous plane with no partitions only guarantees one tie point between the AD82833 and pcb. for more detailed information on packaging and for more pcb layout examples, see the an-772 application note.
AD8283 rev. 0 | page 19 of 28 serial peripheral interface (spi) the AD8283 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. this offers the user added flexibility and customization depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, as documented in the memory map section. detailed operational information can be found in the analog devices, inc., an-877 application note, interfacing to high speed adcs via spi . there are three pins that define the serial port interface, or spi. they are the sclk, sdio, and cs pins. the sclk (serial clock) is used to synchronize the read and write data presented to the device. the sdio (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the devices internal memory map registers. the cs (chip select bar) is an active low control that enables or disables the read and write cycles (see ). table 6 table 6. serial port pins pin function sclk serial clock. the serial shift clock input. sclk is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin. the typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. cs chip select bar (active low). this control gates the read and write cycles. the falling edge of the cs in conjunction with the rising edge of the sclk determines the start of the framing sequence. during an instruction phase, a 16-bit instru ction is transmitted, followed by one or more data bytes, which is determined by bit field w0 and bit field w1. an example of the serial timing and its definitions can be found in and . figure 32 table 7 in normal operation, cs is used to signal to the device that spi commands are to be received and processed. when cs is brought low, the device processes sclk and sdio to process instructions. normally, cs remains low until the communication cycle is complete. however, if connected to a slow device, cs can be brought high between bytes, al lowing older microcontrollers enough time to transfer data into shift registers. cs can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until cs is taken high to end the communication cycle. this allows complete memory transfers without having to prov ide additional instructions. regardless of the mode, if cs is taken high in the middle of any byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port can be configured to operate in different manners. for applications that do not require a control port, the cs line can be tied and held high. this places the remainder of the spi pins in their secondary mode as defined in the sdio pin and sclk pin sections. cs can also be tied low to enable 2-wire mode. when cs is tied low, sclk and sdio are the only pins required for communication. although the device is synchronized during power-up, caution must be exerci sed when using this mode to ensure that the serial port remains synchronized with the cs line. when operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. without an active cs line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb- or lsb-first mode. msb-first mode is the default at power-up and can be changed by adjusting the configuration register. for more information about this and other features, see the an-877 application note, interfacing to high speed adcs via spi . hardware interface the pins described in table 6 constitute the physical interface between the users programming device and the serial port of the AD8283. the sclk and cs pins function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. this interface is flexible enough to be controlled by either serial proms or pic microcontrollers. this provides the user with an alternative method, other than a full spi controller, for programming the device (see the an-812 application note). if the user chooses not to use the spi interface, these pins serve a dual function and are associated with secondary functions when the cs is strapped to avdd during device power-up. see the sdio pin and sclk pin sections for details on which pin- strappable functions are supported on the spi pins.
AD8283 rev. 0 | page 20 of 28 don?t care don?t care don?t care don?t care sdio sclk cs t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 09795-012 figure 32. serial timing details table 7. serial timing definitions parameter minimum timing (ns) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock setup time between cs and sclk t s 5 hold time between cs and sclk t h 2 t hi 16 minimum period that sclk should be in a logic high state t lo 16 minimum period that sclk should be in a logic low state t en_sdio 10 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 32 ). t dis_sdio 10 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 32 )
AD8283 rev. 0 | page 21 of 28 memory map reading the memory map table each row in the memory map table has eight address locations. the memory map is roughly divided into three sections: the chip configuration registers map (address 0x00 and address 0x01), the device index and transfer registers map (address 0x04 to address 0xff), and the adc channel functions registers map (address 0x08 to address 0x2c). the leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. the bit 7 (msb) column is the start of the default hexadecimal value given. for example, address 0x09, the clock register, has a default value of 0x01, meaning that bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 0 of this address followed by an 0x01 to the sw transfer bit in register 0xff, the duty cycle stabilizer turns off. it is important to follow each writing sequence with a write to the sw transfer bit to update the spi registers. note that all registers except register 0x00, register 0x04, register 0x05, and register 0xff are buffered with a master slave latch and require writing to the transfer bit. for more information on this and other functions, consult the an-877 application note, interfacing to high speed adcs via spi . logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. reserved locations undefined memory locations should not be written to except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values after a reset, critical registers are automatically loaded with default values. these values are indicated in table 8, where an x refers to an undefined feature.
AD8283 rev. 0 | page 22 of 28 table 8. AD8283 memory map register addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value default notes/ comments chip configuration registers 00 chip_port_config 0 lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 soft reset 1 = on 0 = off (default) lsb first 1 = on 0 = off (default) 0 0x18 the nibbles should be mirrored so that lsb- or msb-first mode is set correct regardless of shift mode. 01 chip_id chip id bits[7:0] (AD8283 = 0xa2, default) read only the default is a unique chip id, specific to the AD8283. this is a read-only register. device index and transfer registers 04 device_index_2 x x x x x x data channel f 1 = on (default) 0 = off data channel e 1 = on (default) 0 = off 0x0f bits are set to determine which on-chip device receives the next write command. 05 device_index_1 x x x x data channel d 1 = on (default) 0 = off data channel c 1 = on (default) 0 = off data channel b 1 = on (default) 0 = off data channel a 1 = on (default) 0 = off 0x0f bits are set to determine which on-chip device receives the next write command. ff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. channel functions registers 08 global_modes x x x x x x internal power- down mode 00 = chip run (default) 01 = full power- down 11 = reset 0x00 determines the power-down mode (global). 09 global_clock x x x x x x x duty cycle stabilizer 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer on and off (global). 0c flex_mux_control x power- down of unused channels 0 = pd (power- down; default) 1 = power-on x x mux input active channels 0000 = a 0001 = aux 0010 = ab 0011 = a aux 0100 = abc 0101 = ab aux 0110 = abcd 0111 = abc aux 1000 = abcde 1001 = abcd aux 1010 = abcdef 1011 = abcde aux 0x00 sets which mux input channel(s) are in use and whether to power down unused channels.
AD8283 rev. 0 | page 23 of 28 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value default notes/ comments 0d flex_test_io user test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test modesee table 9 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checkerboard output 0101 = pn sequence long 0110 = pn sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the output_mode register) 0x00 when this register is set, the test data is placed on the output pins in place of normal data. (local, except for pn sequence.) 0f flex_channel_input filter cutoff frequency control 0000 = 1.3 1/4 f samplech 0001 = 1.2 1/4 f samplech 0010 = 1.1 1/4 f samplech 0011 = 1.0 1/4 f samplech (default) 0100 = 0.9 1/4 f samplech 0101 = 0.8 1/4 f samplech 0110 = 0.7 1/4 f samplech 0111 = n/a 1000 = 1.3 1/3 f samplech 1001 = 1.2 1/3 f samplech 1010 = 1.1 1/3 f samplech 1011 = 1.0 1/3 f samplech 1100 = 0.9 1/3 f samplech 1101 = 0.8 1/3 f samplech 1110 = 0.7 1/3 f samplech 1111 = n/a x x x x 0x30 low pass filter cutoff (global). f samplech = adc sample rate/ number of active channels. note that the absolute range is limited to 1 mhz to 12 mhz. 10 flex_offset x x 6-bit lna offset adjustment 10 0000 for lna bias high, mid-high, mid-low (default) 10 0001 for lna bias low 0x20 lna force offset correction (local). 11 flex_gain_1 x x x x x 010 = 16 db(default) 011 = 22 db 100 = 28 db 101 = 34 db 0x00 total lna + pga gain adjustment (local) 12 flex_bias_current x x x x 1 x lna bias 00 = high 01 = mid-high (default) 10 = mid-low 11 = low 0x09 lna bias current adjustment (global). 14 flex_output_mode x x x x x 1 = output invert (local) 0 = offset binary (default) 1 = twos comple- ment (global) 0x00 configures the outputs and the format of the data. 15 flex_output_adjust 0 = enable data bits [11:0] 1 = disable data bits [11:0] x x x output drive current 0000 = low 1111 = high (default) 0x0f used to select output drive strength to limit the noise added to the channels by output switching.
AD8283 rev. 0 | page 24 of 28 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value default notes/ comments 18 flex_vref x 0 = internal reference 1 = external reference x x x x 00 = 0.625 v 01 = 0.750 v 10 = 0.875 v 11 = 1.024 v (default) 0x03 select internal reference (recommended default) or ex- ternal reference (global); adjust internal refer- ence. 19 flex_user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 1 lsb. 1a flex_user_patt1_ msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user-defined pattern, 1 msb. 1b flex_user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 2 lsbs. 1c flex_user_patt2_ msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user-defined pattern, 2 msbs. 2b flex_filter x enable automatic low-pass tuning 1 = on (self- clearing) x x 0x00 2c ch_in_imp x x x x x x 0 = 200 (default) 1 = 200k 0x00 input imped- ance adjust- ment (global). table 9. flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 same yes 0010 +full-scale short 1111 1111 1111 same yes 0011 ?full-scale short 0000 0000 0000 same yes 0100 checkerboard output 1010 1010 1010 0101 0101 0101 no 0101 pn sequence long n/a n/a yes 0110 pn sequence short n/a n/a yes 0111 one-/zero-word toggle 1111 1111 1111 0000 0000 0000 no 1000 user input register 0x19 to register 0x 1a register 0x1b to register 0x1c no 1001 1-/0-bit toggle 1010 1010 1010 n/a no 1010 1 sync 0000 0011 1111 n/a no 1011 one bit high 1000 0000 0000 n/a no 1100 mixed bit frequency 1010 0011 0011 n/a no
AD8283 rev. 0 | page 25 of 28 application diagrams pdwn sclk sdio aux muxa zsel dsync notes 1. all capacitors for supplies and references should be placed close to the part. inc+ 0.1f 3.3v avdd33ref 0.1f avdd33a 0.1f avdd33b 0.1f avdd33c 0.1f avdd33d 0.1f avdd33e 0.1f avdd33f 0.1f 3.3v dvdd33spi 0.1f dvdd33clk 0.1f dvdd33drv 0.1f dvdd33drv 0.1f 1.8v avdd18 0.1f avdd18 0.1f avdd18adc 0.1f 1.8v dvdd18 0.1f dvdd18clk 0.1f inc? 0.1f inb+ 0.1f inb? 0.1f ina? 0.1f ina+ 0.1f 10k ? inf+ 0.1f ine+ 0.1f ine? 0.1f inf? 0.1f ind+ 0.1f ind? 0.1f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc dsync pdwn dvdd18 sclk sdio cs aux muxa zsel test1 test2 dvdd33spi avdd18 avdd33a ina? 17 ina+ 18 nc 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 nc nc avdd33b inb? inb+ avdd33c inc? inc+ avdd33d ind? ind+ avdd33e ine? ine+ avdd33f inf? 35 inf+ 36 nc nc test4 dvdd18clk clk+ clk? dvdd33clk avdd33ref vref rbias band apout anout test3 avdd18adc avdd18 inadc+ inadc? nc 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 nc dvdd33drv nc nc d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 dvdd33drv nc AD8283 (top view) cs 09795-013 clk+ clk? inadc+ 0.1f 0.1f 0.1f 10k ? 1% inadc? 0.1f 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 figure 33. differential inputs
AD8283 rev. 0 | page 26 of 28 clk+ clk? pdwn sclk sdio aux muxa zsel dsync notes 1. resistor r (inx? inputs) should match the output impedance of the input driver. 2. all capacitors for supplies and references should be placed close to the part. inc 0.1f 3.3v avdd33ref 0.1f avdd33a 0.1f avdd33b 0.1f avdd33c 0.1f avdd33d 0.1f avdd33e 0.1f avdd33f 0.1f 3.3v dvdd33spi 0.1f dvdd33clk 0.1f dvdd33drv 0.1f dvdd33drv 0.1f 1.8v avdd18 0.1f avdd18 0.1f avdd18adc 0.1f 1.8v dvdd18 0.1f dvdd18clk 0.1f inb 0.1f 0.1f ina inadc+ 0.1f 0.1f 0.1f 10k? 1% 10k ? inadc? 0.1f inf 0.1f ine 0.1f ind 0.1f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc dsync pdwn dvdd18 sclk sdio cs aux muxa zsel test1 test2 dvdd33spi avdd18 avdd33a ina? 17 ina+ 18 nc 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 nc nc avdd33b inb? inb+ avdd33c inc? inc+ avdd33d ind? ind+ avdd33e ine? ine+ avdd33f inf? 35 inf+ 36 nc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 nc test4 dvdd18clk clk+ clk? dvdd33clk avdd33ref vref rbias band apout anout test3 avdd18adc avdd18 inadc+ inadc? nc 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 nc dvdd33drv nc nc d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 dvdd33drv nc AD8283 (top view) cs 09795-029 0.1f r figure 34. single-ended inputs
AD8283 rev. 0 | page 27 of 28 outline dimensions compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.90 0.85 0.80 0.70 0.65 0.60 0.05 max 0.01 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.60 8.50 sq 8.40 8.50 ref exposed pad (bottom view) top view 9.75 bsc sq 10.00 bsc sq pin 1 indicator seating plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indicator coplanarity 0.08 forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.25 min 07-26-2010-c figure 35. 72-lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp-72-5) dimensions shown in millimeters ordering guide model 1 , 2 , 3 temperature range package description package option AD8283wbcpz-rl ?40c to +105c 72-lead lfcsp_vq, 13 tape and reel cp-72-5 AD8283wbcpz ?40c to +105c 72-lead lfcsp_vq, waffle pack cp-72-5 1 z = rohs compliant part. 2 w = qualilfied for automotive applications. 3 compliant to jedec standard mo-220-vnnd-4. automotive products the AD8283wbcpz models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; ther efore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are a vailable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for this model.
AD8283 rev. 0 | page 28 of 28 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09795-0-4/11(0)

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